Capacitor having improved electrodes

ABSTRACT

Capacitor material for use in forming capacitors, is disclosed. More specifically, the invention is directed to capacitors formed from this material that have one or more discrete electrodes ( 314 ), each electrode ( 314 ) being exposed to at least two thicknesses of dielectric material ( 300 ). These electrodes ( 314 ) are surrounded by wider insulative material ( 312 ) such that the material can be cut, or patterned into capacitors having specific values. A single electrode can form a small value capacitor while still providing a larger conductive area for attaching the capacitor to associated circuitry. The thin dielectric ( 310 ) can be a tunable material so that the capacitance can be varied with voltage. The tunability can be increased by adding thin electrodes that interact with direct current.

This application claims the benefit of U.S. Provisional application Ser.No. 60/290,122 filed May 10, 2001.

FIELD OF THE INVENTION

The present invention is directed to capacitors. In particular, theinvention is directed to capacitors having one or more discreteelectrodes, the electrodes being formed such that one of the capacitorconductor surface areas extending to the thin film dielectric is muchsmaller than the conductor surface area in the zone of the thickerdielectric. In these structures, the capacitance is dominated by thethinner dielectric, and the voltages required for producing changes inparaelectric, ferroelectric and other electrically affected materialcharacteristics, are minimized. The invention also includes severalembodiments of electrodes formed on supporting substrates and bulkdielectrics.

BACKGROUND OF THE INVENTION

Parallel plate capacitors have been in manufacture for many years. Thebasic design of these capacitors involves two conductive electrodesseparated by a dielectric or insulative thin film material. While manyvariations of this type of capacitor have been developed, all of theknown designs suffer from the following disadvantages. One of thesedisadvantages is the condition wherein a small defect in the dielectriclayer wherein the two electrodes are allowed to short together. Thisshort circuit renders the entire capacitor useless, resulting in loss ofproduct. A second disadvantage is the inability to take a single sheetof capacitor material (formed of a sandwich of conductive material onthe outside and thin film dielectric material on the inside), and cutthis material into several smaller value capacitors and attachingconnectors to the conductive portions of these smaller value capacitors.This inability is due to the shorting out of the conductive layers bythe cutting, shearing or connecting action itself that creates defectsin the dielectric, resulting in high leakage and potential shorts. Thepresent invention overcomes these disadvantages by providing discretelocations of electrode interaction, thereby allowing failure points tobe removed, as well as allowing a simple method of forming capacitorswith specific capacitance. Furthermore, due to the reduced activeelectrode area, capacitors with small capacitance can be formed whilestill allowing enough surface area for connecting the capacitor to othercircuitry. These thin dielectrics, if ferroelectric, such as bariumstrontium titanate (BST), can have the capacitance varied by applying abias voltage. The thinner the dielectric, the lower the bias voltage canbe to effect the same capacitance change. These tunable capacitors havea wide range of applications particularly in the RF wireless arena.

In the field of tunable capacitors that use ferroelectric dielectrics, aparticular problem is intermodulation distortion (IMD), that can occuras the RF electric field inadvertently biases the material at the RFfrequency. This problem is addressed by the present invention byproviding several embodiments of capacitor electrodes that allow greaterlevels of tunability, while reducing RF interaction with the biasingelectrodes.

SUMMARY OF THE INVENTION

The present invention is directed to several embodiments of capacitorseach of which includes one or more electrodes, that are exposed to oneor more dielectric layers. One method of forming the capacitor is byfirst depositing a thin dielectric material having a relatively highdielectric constant (k) (preferably BST) onto a conductive metalsubstrate (such as nickel). A layer of insulative material (such asglass or epoxy) with a relatively low dielectric constant (k) is thendeposited on top of the dielectric material. The insulative material isthen selectively etched to remove material from electrode sites. Theelectrode sites are preferably circular but may be other shapes as well.The diameter of the sites are on the order of about 1–40 μm, mostpreferably 4–15 μm. Once the insulative material has been removed fromthe sites, a top layer of metal (such as copper) is deposited on theinsulative material. This metal fills the sites thereby sandwiching thethin film dielectric between the site (electrode) and the bottomconductive material to form a capacitor. It should be understood thatthe capacitor or insulator material can be formed by other methods suchas silk screening the insulative layer to form the sites. In addition,the dielectric material may initially be deposited on a non-conductivesubstrate, and the substrate can be removed after the top layers havebeen deposited and then a conductive material can be deposited on thedielectric material. This may be useful to allow formation of epitaxialdielectrics by using an initial, non-conductive epitaxial substrate(such as sapphire) and then replacing the sapphire with copper or othernon-epitaxial conductors after formation of the dielectric.

Alternatively, the thick dielectric can be formed as a conductor, andspires of conductor can be formed to the surface of the thickdielectric. Methods of forming these spires or “nanostructures” can befound in U.S. Pat. No. 6,372,364, entitled “NANOSTRUCTURE COATINGS,which issued to Hunt et al. on Apr. 16^(th), 2002, and is herebyincorporated by reference. The thin dielectric can be formed across boththe conductive spire ends and the thick dielectric, or selectively juston the conductor. A conductor is then formed over this surface. The endresult is the same as a product having a capacitance defined by the muchsmaller (but much closer) electrode surface.

Another important factor is the robustness of the end device. If thefirst conductor is metal or more specifically metal foil, and the thindielectric is ceramic, then the interfaces between the ceramic and metalcan be potential points of failure, as is well understood in the art. Byforming high adhesion materials on the dielectric that are thicker andmore robust, (even self supporting if formed independently of the otherlayers or components), the result is a more robust product. Thecapacitance for a specific area is a function of thickness anddielectric constant. Therefore, the thinner the dielectric compared tothe insulator, (>3 times thinner, >10 times thinner and preferably >20times thinner), the higher the capacitance from the thin dielectric fora given device. Furthermore, the dielectric should have at least as higha dielectric constant as the insulator, preferably >2 times higher, 5times higher or most preferably more than 10 times higher, particularlywhen these layers have similar or close thicknesses compared to eachother.

The discrete electrodes formed by filling the sites with conductivematerial are preferably arranged in an array. By forming the electrodesin an array, it is easier to divide, pattern or slice the material alonglines that do not intersect the electrodes. In this manner, thedividing, patterning or slicing takes place at points that includerelatively thick portions of insulative material, thereby reducing thechances of shorting out the two conductive layers. Defining the materialinto smaller pieces reduces the number of and/or area of the plates andtherefore the capacitance of the sheet. The resulting capacitor mayinclude as little as a single site to form a small value capacitor, or anumber of sites for higher capacitance, while still allowing a largersurface area (the conductive top and bottom layers) for attachment toassociated circuitry.

In a further embodiment, one or more additional conductive materiallayer(s) are provided. This layer or layers are formed of a firstconductive material that has a relatively low conductivity, while theconductive material of the electrode sites and connecting the electrodesites, is formed of a second conductive material that has a relativelyhigh conductivity. This is particularly useful in tunable capacitorsused in RF applications. The lower conductivity material has a slowerresponse to applied electric fields between the top and bottomconductors. Therefore, the DC (or low frequency AC) biasing voltagecreates a stronger electric field through the tunable dielectric thenthe applied RF signal. Lower tuning voltages can be used to create therequired change in the dielectric material, while the RF signal isapplied across a larger distance. As is known, when the RF signalaffects the dielectric constant of the material, intermodulationdistortion (IMD) can occur. By reducing the strength of the applied RFelectric field compared to the DC field, low tuning voltages areachieved with reduced interaction of the RF field. Conductivity of thematerial is dependent on the number of charge carriers, and the chargecarrier mobility. By forming the additional layers from a materialhaving a low charge carrier mobility, the additional layers can be usedas electrodes to apply the DC biasing signal over a small distance(large effective electric field), while resisting the voltage of theapplied RF signal (as the charge carriers cannot react to the speed ofthe changing RF signal). The formation of these “low-loss” electrodes ismore fully described in International Patent Application No.PCT/US01/26491, published on Feb. 28^(th), 2002 as WIPO Publication No.WO 02/16973, entitled “ELECTRONIC AND OPTICAL DEVICES AND METHODS OFFORMING THESE DEVICES” and hereby incorporated by reference in itsentirety.

The terms “low loss” and lower conductivity, as applied to the capacitorelectrodes of the present invention are defined herein as materials thathave a low charge carrier mobility or a reduced number of chargecarriers (charge carrier density). The conductivity of a material isequal to the electronic charge times the charge carrier mobility timesthe charge carrier density (for both electrons and holes). In some ofthe embodiments of the capacitor electrodes of the present invention, itis preferred that the low conductivity material has a low charge carriermobility (less than 10 cm²/V·s, preferably less than 5 cm²/V·s and mostpreferred less than 0.10 cm²/V·s). In other embodiments it is preferredthat the charge carrier mobility be relatively high (preferably greaterthan 30 cm²/V·s, more preferably greater than 100 cm²/V·s, and mostpreferred greater than 1000 cm²/V·s), while the “available” chargecarrier density is controlled. The term “available”, relates to theability of the RP signal to interact with the charge carriers. Some ofthe embodiments included herein control the availability of these chargecarriers to the RF signal by using a DC of low frequency AC bias to“lock” these charge carriers in place. Preferably 30%, 50% or more ofthe total charge carriers can be controlled in this manner, thus theavailable charge carrier density is 70%, 50% or less of the total chargecarrier density. In some embodiments, the specific mechanisms areirrelevant and the low conductivity material can be defined in terms ofits resistivity. Preferably this resistivity is 100 Ω/square or less.

These low-loss electrodes have further utility in other embodiments ofthe capacitor of the present invention that use bulk dielectricmaterial. By forming low loss interdigital electrodes on a surface of abulk dielectric, the advantages of the low loss electrodes can beapplied to relatively inexpensive dielectric material that iscommercially available in bulk form. While the DC biasing electric fieldand the RF electric field may only permeate partially through thedielectric material, the advantages of low-loss, tunability, and reducedIMD, are still possible. Besides the reduced cost of the dielectricmaterial, another advantage of using the bulk dielectric is reducedmanufacturing steps as described below with reference to the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-section of an electrode of the capacitor materialof the present invention.

FIG. 2 shows a top view of the capacitor material of FIG. 1.

FIGS. 3 a–3 h illustrate one method of producing the capacitor materialof FIG. 1.

FIGS. 3 i and 3 j show further embodiments of the capacitor material ofFIG. 1.

FIG. 4 shows a cross section through a further embodiment of thecapacitor material of the present invention.

FIG. 5 shows a top view of another embodiment of the capacitor material.

FIGS. 6–11 show the steps in forming dielectric and electrode structureson a substrate, in accordance with a method of the present invention forforming electronic and optical devices.

FIG. 12 shows another embodiment of the structures of FIGS. 6–11.

FIGS. 13–17 show further embodiments of the electrodes of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention may be understood more readily by reference to thefollowing detailed description of preferred embodiments of the inventionand the figures.

FIG. 1 is a cross-sectional view through an electrode site in thelaminate capacitor material 10 of the present invention. A conductivesubstrate 12 is coated with a layer of dielectric material 14 having,preferably, a relatively high dielectric constant (k). On top of thedielectric material 14 is a layer of insulative material 16 or materialhaving a relatively low dielectric constant (k). The insulative material16 is either not deposited or removed from the electrode site 11, aspreviously described. Conductive material 18 is then coated on top ofthe insulative material 16 and fills the voids at the site 11 locations.Alternatively, the electrodes are formed first, and then the insulatoris filled in. In this manner, discrete capacitors are formed betweenelectrode layers 18 and 12 at the site 11 locations. Each site 11 has adiameter D on the order of 1–40 μm, and more preferably about 4–15 μm.At the site 11 locations, the electrode layers 12 and 18 (which includesthe material of site 11) are closer together (on the order of 50–5000nanometers, preferably 100–1000 nanometers, most preferably 150–500nanometers) with only the high k material layer 14 between them. At allother locations, the electrode layers 12 and 18 are separated by theinsulative layer 16 as well as the dielectric layer 14. The thickness ofthe dielectric material 14 and the insulative material 16, is >3 timesthicker (150 nm–15,000 nm), >10 times thicker (500 nm–50,000 nm) andmost preferably >20 times thicker (1000 nm–100,000 nm) than thedielectric layer 14 alone. Thus a plurality of discrete capacitors areformed at the site locations 11 with little or negligible capacitance(<25%, <5% or preferably <1%) being contributed by the other portions ofthe laminate material 10. The total surface area of the dielectricmaterial 14 (which is substantially the same as the area of theelectrode layer 18) is preferably greater twice the total surface areaof all the electrode sites 11 that contacts the dielectric material 14,and more preferably is 5, 10, 20 or most preferably 50 times greater.

FIG. 2 shows a top schematic view of the laminate material 10, with thesite 11 locations being illustrated for discussion purposes only (theselocations would not appear as sharp transitions through conductive layer18, but rather as dimples in conductive layer 18). Each site 11functions as a discrete capacitor in parallel with all of the othersites 11 to form a capacitor array with a capacitance equal to all ofthe discrete capacitors' capacitance added together. By cutting thematerial into sections (as shown by dotted line 22) a capacitor 24 ofspecific capacitance can be formed. As shown, the cutting line 22 isformed between sites 11 to reduce the chance of shorting the twoconductive layers 12 and 18 together as previously described. Inaddition, should a particular site (shown for example as 11′) fail(short out) then this site (or other failed area) can be removed. Onemethod of removal is by cutting or punching out the area as shown bydotted line 26.

FIGS. 3 a–3 h show steps of one particular method of producing thecapacitor material of the present invention, it being understood thatthere are a number of other methods equally capable of producing theinvention. FIG. 3 a shows a dielectric material with a relatively highdielectric constant (for example, BST) 300 deposited on a substrate Smade of a suitable material. The substrate is preferably a goodconductor such as copper, gold or platinum. Other materials may be usedas well (such as sapphire or textured nickel to aid in epitaxial growthof the upper layers, if needed), and it should also be understood thatsubstrate S may be removed after deposition of the other layers, and aconductor can be deposited in its place. On top of the dielectricmaterial 300 is a first, optional layer 302 and a second seed layer 304.Seed layer 304 is formed of conductive material (such as Cu, Pt, Ag,etc.), while optional layer 302 is formed of a material (Cr, SiO2, etc.)that aids in adhesion of layers 304 and 300, but need not necessarily beconductive. Another optional layer may be used between substrate S anddielectric layer 300 to aid in adhesion between these layers. In FIG. 3b, a layer of photoresist 306 is show deposited on top of layer 304,with the photoresist removed from locations where electrode sites willbe formed. As shown in FIG. 3 c, additional conductive material 308 isdeposited on the exposed portions of seed layer 304 using electroplating(layer 304 being conductive) or other suitable deposition techniques.Once the additional conductive material 308 has been deposited, thephotoresist 306 can be removed as shown in FIG. 3 d. A flash etch isthen used to remove those portions of layers 302 and 304 not protectedby the additional conductive material 308 (those portions between theelectrode sites). As layers 304 may be formed of the same material asthe additional conductive material 308, the flash etch may remove someof the additional material 308, although this should be negligible, ormay be considered when determining the thickness of material 308 to bedeposited. Also alternatively, the photoresist 306 can be applied priorto the seed layer 304, and any conductive material deposited on thephotoresist 306, will be removed when the photoresist 306 is removed insubsequent processing steps. Further if the optional layer 302 is thinenough, it may be left in, as can the photoresist 306 if it is stableand acts as an insulator. In these ways, the number of processing stepscan be reduced.

After removing the portion of layers 302 and 304 between electrodesites, a thicker insulator, preferably, with a relatively low dielectricconstant 312 is deposited in the spaces between the electrode sites(note that all the conductive material is labeled as 310 in FIGS. 3 f–3h, for clarity). While the resistive material 312 is primarily depositedbetween electrode sites, some of this material may form a thin layer ontop of conductive material 310. FIG. 3 g shows the conductive material310 and the insulative material 312 after the top has been shaved(possible using chemical and/or mechanical polishing (CMP) to removeinsulative material from the tops of the electrodes. A final layer ofconductive material 316 is then deposited to electrically join all ofthe electrodes, as shown in FIG. 3 h.

FIGS. 3 i and 3 j illustrate further embodiments of the capacitormaterial of FIGS. 3 a–3 h. The same steps in forming the material andelectrodes 310, as described above with respect to FIGS. 3 a–3 h, can beused to form the material in FIGS. 3 i and 3 j. The material in FIGS. 3i and 3 j, however, includes one or more conductive layers 314, that aredeposited within the dielectric material 300 (for example, byalternating deposition of the material of layers 314 and the material oflayer(s) 300). Layers 314 are preferably formed of relatively low RFinteractive material as described above in the summary of the invention.This low conductivity material 314 has a relatively low charge carriermobility when compared to the material of layer 316 and electrodes 310.Thus the DC (or low frequency AC) biasing signal is applied betweenlayers 316 and 314 or 314 and S (for a single layer 314 as shown in FIG.3 i) or between the layers 314 (as shown in FIG. 3 j). Therefore, the DCelectric field is applied over distance d_(DC), while the RF signalelectric field is applied over distance d_(RF). This results in agreater DC field to adjust the dielectric constant of electricallyadjustable dielectric material 300, with a weaker RF field to avoidaffecting the dielectric constant at an RF rate (that can cause IMD).The low conductivity material of layers 314 also helps to reduceinteraction with the RF signal.

In FIGS. 4 and 5, further embodiments of the capacitive material ofFIGS. 1 and 2 are shown. As with the previous embodiment, material 40includes a conductive substrate 42 coated with a layer of dielectricmaterial 44 having a relatively high dielectric constant (k). On top ofthe dielectric material 44 is a layer of insulative material 46 ormaterial having a relatively low dielectric constant (k). The insulativematerial 46 is either not deposited or removed from the electrode site41, and conductive material 48 is deposited thereon to form theelectrode sites 41′, 41″ and 41′″, each having a different diameter, D′,D″ and D′″, respectively. Further, the spacing between the electrodesites may also vary as shown by S′ and S″. In contradistinction to theembodiment of FIGS. 1 and 2, the electrode sites 41′, 41″ and 41′″ arenot electrically connected to one another. The top electrode layer ispattern plated to provide each site with its own distinct top pad. Byvarying the spacing and diameter of the electrode sites, a material 50as shown in FIG. 5 can be formed. Material 50 has a plurality ofelectrode sites 51, 51′, 51″ and 51′″ each having a different effectivediameter. The tops of each of the electrode sites include, a conductivepad 53, that is shown here as having a square shape, although circularor other shapes would work as well. The pads 53 are shown as similar insize, although they may vary as long as they are all large enough to beelectrically connected to one another using jumpers (or simply solder).By cutting the material 50 into different sections (for example as shownby dotted lines 52, a number of mechanically adjustable capacitors 54are formed. Each capacitor 54 can then be adjusted by attaching the padsof several electrode sites together. Because each site has a differentcapacitance, they can be added together to form the desired overallcapacitance.

FIGS. 6–11 illustrate a method of forming dielectric and electrodestructures according to another aspect of the present invention. A layerof dielectric material 72 (such as BST) is first deposited on asubstrate 70 (such as sapphire). A layer of photoresist 80 is thendeposited on top of those portions of the dielectric layer 72 that areintended to remain. The remainder of the dielectric material (notcovered by the photoresist 80) is then etched away using a suitableetchant for the particular dielectric material used. A layer ofconductive material 1000 (such as copper) is then deposited on top ofthe structure (FIG. 9). It should be noted that it is not necessary toremove the photoresist 80 prior to depositing the conductive material1000. The top of the conductive layer is then etched to remove theportion on top of the photoresist layer 80 to thereby form the distinctelectrodes 1000 as shown in FIG. 10. In FIG. 11 the optional step ofremoving the photoresist 80 is illustrated. It should be understood thatthe photoresist 80 may be left intact as it does not affect theoperation of most devices. In fact, the photoresist 80 may add strengthto the structure. The main advantage of this method is the reducednumber of steps to produce the device or devices. A single masking stepis required, by simply etching the electrode material to the level ofthe mask (photoresist layer 80), unwanted conductive material isremoved.

FIG. 12 illustrates a further embodiment of an electrode and dielectricstructure for use in optic and RF applications. In this device, aportion of the dielectric material 72 extends under the electrodes 1000as shown at points 1300. By extending the electrodes 1000 over the topof the edges of the dielectric, more of the applied electric fieldbetween the electrodes may permeate the dielectric, therefore creating alarger change on the dielectric constant/index of refraction inferroelectric/electrooptic materials. Another advantage of thestructures of FIGS. 11 and 12 over prior art devices involves adhesionof the electrodes to the device. In prior art devices, often thedielectric layer completely covers the substrate, and the electrodes arepattern plated on top of the dielectric material. Some conductors (suchas chrome, gold and copper) have adhesion problems when deposited on topof certain dielectrics (such as BST). By patterning the dielectric, theelectrode material is predominately deposited directly onto thesubstrate, thus the adhesion problems between the conductors and thedielectric layer can be minimized.

In FIG. 13, a further embodiment of the improved electrodes of thepresent invention is shown in connection with capacitor 130. Capacitor130 is formed by depositing (or otherwise attaching) RF electrodes 136and biasing electrodes 134 on top of a bulk dielectric material 132.Bulk dielectric material is commercially available and can be obtainedas tunable material (such as BST) or non-tunable material. In a parallelplate configuration, bulk dielectric material is difficult to use toform higher value capacitors, as the increased thickness of the material(d), reduces the overall capacitance of the capacitor (capacitance isproportional to A/d, where A is the area of the plates and d is thedistance between the plates). In the present capacitor, interdigitalfingers 134 are used, so the distance between the fingers (d) can bemade quite small (less than 10 microns, preferably less than 5 micronsand most preferred, less than 1 micron). The number of fingers can beincreased to increase the area of the fingers facing one another. Bulkmaterial 132 can be thick (0.5 mm, 1 mm and even greater than 5 mm)without affecting the performance of the capacitor. Obviously, the RFand biasing electric fields will only permeate into the top portion ofthe bulk material 132, but this is adequate for increasing thecapacitance and/or the adjustability of the device. Biasing electrodes134 are straight and predominately parallel to the RF electrodes 136,such that the biasing electric field and the RF electric field arepredominately parallel in the region of the biasing electrodes 134.

Biasing electrodes 134 are preferably formed of relatively lowerconductivity (low charge carrier mobility and/or number of chargecarriers) material. Preferably this lower conductivity material has aresistance of more than 100 Ω/square. RF electrodes 136 are formed ofrelatively higher conductive material. Due to the closer spacing of thebiasing electrodes 134, the electric field from the DC (or low frequencyAC) biasing signal is stronger than the electric field induced by the RFsignal. If the resistivity of the low conductivity material ispredominately caused by reduced charge carrier mobility, the RF signalchanges too fast to move the low mobility charge carriers in fingers134. Thus tunability can be achieved, without introducing undesired IMD.

In FIG. 14, a further embodiment of a capacitor 140 using the relativelylower conductivity material is shown. Alternating layers of dielectricmaterial 142 and lower conductivity material 144 are formed byalternating deposition (horizontally as shown) or other known methods.RF electrodes 146 are then deposited on top as shown. As in the previousembodiments, the RF electrodes exert the RF electric field over agreater distance, while the DC electric field is exerted over a smallerdistance (between layers 144). Layers 144 may be formed with other,better conductors, as low conductivity material will decrease RFinteraction, but high loss can be associated with thick layers of lowcharge carrier mobility material.

In FIGS. 15–17, top views of RF electrodes 152 are shown on a bulkdielectric 154, with three different embodiments of additionalelectrodes or dielectric enhancing material. In these embodiments, thelow conductivity material of the biasing electrodes has a high mobility,but a controlled number of charge carriers. The biasing electrodes notonly help to apply the tuning voltage, but also provide dipoles that canincrease the effective dielectric constant between the RF electrodes.The DC bias not only tunes the dielectric material (if tunable), butlocks the limited charge carriers (dipoles) of the electrodes in place,resulting in a lower “artificial dielectric effect.” This results inproviding an even greater degree of tuning.

In FIG. 15, the additional electrodes 156 are in the form ofinterdigital fingers. Electrodes 156 are formed of a high charge carriermobility material that has a limited number of charge carriers. The highcharge carrier mobility material enhances the dielectric constant of thedielectric 154. Because of the reduced number of charge carriers,however, this effect is reduced when the DC field is applied betweenelectrodes 156. The distance between the RF electrodes 152 is muchgreater than the distance between the DC electrodes 156, providing theadvantages described above with reference to the other embodiments.

In FIG. 16, electrode 160 is also formed of high charge carrier mobilitymaterial that has a limited number of charge carriers. Using selectivedeposition, or etching, windows 162 are formed in electrode 160, tofurther limit the number of charge carriers. When a DC bias is appliedbetween one of the RF electrodes 152 (shown as the right) and electrode160, the DC field is again applied over a much shorter distance (d_(DC))than the distance between the RF electrodes. The DC field also helps tolock some of the charge carriers in place to reduce the dielectricenhancement normally provided by the high charge carrier mobilitymaterial.

In FIG. 17, a much simpler embodiment of FIG. 16 is shown. Thisdescription of FIG. 16 is identical to that of FIG. 17 except thatelectrode 170 has amore limited number of charge carriers, andtherefore, the windows 162 of FIG. 16 are not needed. Alternatively, thecenter portion or portions of the sheet 170 are etched or selectivelydeposited with less material than the edges of the sheet proximate tothe RF electrodes. This has much the same effect as forming windows 162.

1. A multi-layer material for forming at least one capacitor, saidmaterial comprising: a first continuous layer of conductive material; asecond continuous layer of material having a relatively high dielectricconstant; a third layer having conductive regions and insulativeregions, said conductive regions being formed of conductive material toform electrode sites, said insulative regions being formed about andbetween adjacent electrode sites; and a fourth layer of conductivematerial electrically connected to said conductive material in theelectrode sites; wherein said electrode sites have a first area, andsaid fourth layer has a second area, and said second area is at leasttwice said first area.
 2. The material of claim 1, wherein said secondlayer is between 100 nm and 1 micron in thickness.
 3. The material ofclaim 1, wherein said second layer is between 150 nm and 500 nm inthickness.
 4. The material of claim 1, wherein said third layer is atleast 10 times thicker than said second layer.
 5. The material of claim1, wherein each of the electrode sites have a diameter between 4 and 15microns.
 6. The material of claim 1, wherein the material has an overallcapacitance, and the amount of capacitance provided by said electrodesites is at least 75% of the overall capacitance of the material.
 7. Thematerial of claim 1, wherein the material has an overall capacitance,and the amount of capacitance provided by said electrode sites is atleast 99% of the overall capacitance of the material.
 8. The material ofclaim 1, wherein said second layer is made of a voltage tunabledielectric material.
 9. The material of claim 1, further comprising atleast one layer of low conductivity material within said second layer.10. The material of claim 9, wherein said low conductivity material hasa charge carrier mobility of less than 10 cm²/V·s.
 11. A capacitor withat least one electrode, said electrode having a surface with a firstportion adjacent to a thin dielectric and a second portion exposed to athicker insulator, wherein the capacitor has an overall capacitance, andthe amount of capacitance provided by said first portion is at least 95%of the overall capacitance of the capacitor.
 12. The capacitor of claim11, wherein the capacitor has an overall capacitance, and the amount ofcapacitance provided by said first portion is at least 99% of theoverall capacitance of the capacitor.
 13. The capacitor of claim 11,wherein the second portion is at least 20 times larger in area than saidfirst portion.
 14. A printed wiring board comprising a capacitor with atleast one electrode, said electrode having a surface with a firstportion adjacent to a thin dielectric and a second portion exposed to athicker insulator, wherein the capacitor has an overall capacitance, andthe amount of capacitance provided by said first portion is at least 75%of the overall capacitance of the capacitor.
 15. The printed wiringboard of claim 14, wherein the capacitor has an overall capacitance, andthe amount of capacitance provided by said first portion is at least 95%of the overall capacitance of the capacitor.
 16. The printed wiringboard of claim 14, wherein the thin dielectric is between 100 nm and 1micron in thickness.
 17. An electrical device or component containing acapacitor with at least one electrode, said electrode having a surfacewith a first portion adjacent to a thin dielectric and a second portionexposed to a thicker insulator, and said capacitor being bonded to orcontained within said electrical device or component, wherein thecapacitor has an overall capacitance, and the amount of capacitanceprovided by said first portion is at least 75% of the overallcapacitance of the capacitor.
 18. The electrical device or component ofclaim 17, wherein the capacitor has an overall capacitance, and theamount of capacitance provided by said first portion is at least 95% ofthe overall capacitance of the capacitor.
 19. The electrical device orcomponent of claim 17, wherein the capacitor has an overall capacitance,and the amount of capacitance provided by said first portion is at least99% of the overall capacitance of the capacitor.
 20. A laminate materialfor forming at least one capacitor, said material comprising: a firstcontinuous layer of conductive material; a second continuous layer ofmaterial having a relatively high dielectric constant; a third layerhaving conductive regions and insulative regions, said conductiveregions being formed of conductive material to form electrode sites,said insulative regions being formed about and between adjacentelectrode sites; and a fourth layer having conductive regions andinsulative regions, said conductive regions of said fourth layer eachbeing electrically connected to one of said electrode sites; whereinsaid conductive regions in said fourth layer can be selectivelyconnected to one another to thereby form capacitors with a desiredcapacitance.
 21. The material of claim 20, wherein said second layer isbetween 100 nm and 1 micron in thickness.
 22. The material of claim 20,wherein each of the electrode sites have a diameter between 1 and 40microns.
 23. The material of claim 20, wherein each of the electrodesites have a diameter between 4 and 15 microns.
 24. The material ofclaim 20, wherein the material has an overall capacitance, and theamount of capacitance provided by said electrode sites is at least 99%of the overall capacitance of the material.
 25. A capacitor comprising:a dielectric material having a surface; a first RF electrode formed onsaid surface; a first biasing electrode formed on said surface; a secondbiasing electrode formed on said surface; and a second RF electrodeformed on said surface; wherein said first RF electrode is spaced afirst distance from said second RF electrode; said first biasingelectrode is spaced a second distance from said second biasingelectrode; said first distance is greater than said second distance; andsaid RF electrodes form interdigital fingers with one another and saidbiasing electrodes form interdigital fingers with one another.
 26. Thecapacitor of claim 25 wherein said dielectric material has a thicknessof 1 mm or greater.
 27. The capacitor of claim 25 wherein said biasingelectrodes are formed of a conductive material having a resistance of100 Ω/square or greater.
 28. The capacitor of claim 25 wherein saidsecond distance is less than 5 microns.
 29. The capacitor of claim 25wherein said biasing electrodes are straight.
 30. The capacitor of claim25 wherein said biasing electrodes are predominately parallel to said RFelectrodes, such that an applied biasing electric field and an appliedRF electric field are predominately parallel to one another in theregion of the biasing electrodes.
 31. A capacitor comprising: adielectric material portion; a first RF electrode on said dielectricmaterial portion; a second RF electrode on said dielectric materialportion; and at least one layer of lower conductivity material withinsaid dielectric material portion and between said RF electrodes.
 32. Thecapacitor of claim 31 wherein said dielectric material is tunable, and abias voltage is applied between said at least one layer of lowerconductivity material and at least one of said RF electrodes.
 33. Thecapacitor of claim 31 wherein said at least one layer of lowerconductivity material comprises at least two layers of lowerconductivity material; said dielectric material is tunable and a biasvoltage is applied between said at least two layers of lowerconductivity material.
 34. A capacitor comprising: a bulk dielectricmaterial having a surface; a first RF electrode formed on said surface;at least one biasing electrode formed on said surface; and a second RFelectrode formed on said surface; wherein said first RF electrode isspaced a first distance from said second RF electrode; said at least onebiasing electrode is spaced a second distance from one of said RFelectrodes; said first distance is greater than said second distance;and said at least one biasing electrode is formed of a low conductivitymaterial having a charge carrier mobility of greater than 30 cm²/V·s anda controlled charge carrier density.
 35. The capacitor of claim 34wherein said at least one biasing electrode comprises two biasingelectrodes.
 36. The capacitor of claim 34 wherein said at least onebiasing electrode has at least one edge proximate to said RF electrodes,and said edge includes more low conductivity material than the remainderof said at least one biasing electrode.
 37. The capacitor of claim 34wherein said sheet includes several holes or windows that do not containsaid low conductivity material.
 38. The capacitor of claim 34 whereinwhen a bias voltage is applied to said at least one biasing electrode,said controlled charge carrier density is 70% of the total availablecharge carriers.